1. Field
The present invention relates to a nonvolatile semiconductor memory device having a gate electrode structure configured with an insulating film being interposed between a charge storage layer and a control electrode, and a method of fabricating the same.
2. Related Art
Conventional nonvolatile semiconductor memory devices have a gate electrode structure of each memory cell configured with an insulating film being interposed between a charge storage layer and a control electrode in order that information may be stored in a nonvolatile manner. U. S. Patent Application Publication, US2008/0121972 discloses a technical idea that an intergate insulating film (corresponding to a second insulating film) is formed on a first gate electrode layer (corresponding to a charge storage layer). In this case, a silicon nitride film is selectively formed on an exposed surface of the first gate electrode layer, whereby the silicon nitride film is divided on an element isolation insulating film. As a result, interference between a plurality of memory cells is suppressed as much as possible.
US2008/0121972 discloses in paragraph 0034 that the silicon nitride film has a film thickness of about 1 nm in order that a silicon nitride film serving as a lowermost layer may selectively be formed only on the exposed surface of the first gate electrode layer. Furthermore, U.S. Patent Application Publication, US2008/0067576 discloses a similar fabricating method. However, the disclosed structure is insufficient to improve the threshold voltage characteristic of a memory cell.
US2008/0067576 further discloses a fabricating method in which a silicon nitride film on an element isolation insulating layer is caused to disappear by diffusing an oxidizing agent in the element isolation insulating layer particularly when an oxidizing treatment is applied to sidewalls of the gate electrodes after the forming of a silicon nitride film serving as the lowermost layer of the intergate insulating film. In the disclosed technical idea, however, the aforesaid sidewall oxidizing process is executed after a control electrode has been stacked on the intergate insulating film and an electrode structure including the control electrode has been divided. Accordingly, the sidewall oxidizing process is executed after the forming of a stacked structure of a silicon oxide film and a silicon nitride film constituting the intergate insulating film. It is difficult to effectively remove only the silicon nitride film which constitutes the intergate insulating film and is formed directly on the element isolation insulating layer. As a result, there is a possibility that prevention of interference between adjacent memory cells may become insufficient.